At ISSCC 2024, Samsung doubled DDR5 capacity using a symmetric-mosaic architecture, enabling 32Gb monolithic DDR5 chips at 8.0Gb/s/pin. This breakthrough allows 128GB modules without TSV, reduces power by 10%, and fits higher density into standard form factors-meeting the surging demands of AI and data centers.
How Does Samsung’s Symmetric-Mosaic Architecture Double DDR5 Capacity?
Samsung’s symmetric-mosaic architecture, unveiled at ISSCC 2024, splits each logical memory bank into ⅓ and ⅔ partitions, interleaving them in a mosaic layout. This approach enables a 32Gb DDR5 monolithic die-doubling capacity compared to the previous 16Gb standard-without expanding the chip’s footprint beyond standard form factors. By sharing global I/O lines and sense amplifiers between partitions, Samsung reduces I/O capacitance, boosting speed and lowering power consumption.
Chart: Comparison of DDR5 Capacity and Architecture
| Feature | Traditional DDR5 (16Gb) | Symmetric-Mosaic DDR5 (32Gb) |
|---|---|---|
| Max Capacity/Module | 64GB–128GB | 128GB–1TB |
| Bank Organization | Uniform | Symmetric-Mosaic |
| TSV Needed? | Yes (128GB+) | No (128GB) |
| Power Consumption | Baseline | ~10% Lower |
| I/O Speed (per pin) | Up to 6400Mbps | Up to 8000Mbps |
What Are the Technical Innovations Behind Samsung’s ISSCC 2024 DDR5 Chip?
Samsung’s ISSCC 2024 DDR5 chip employs a monolithic 32Gb die built on a 5th-generation 10nm process. The symmetric-mosaic architecture allows two partitions from different logical banks to share global I/O and sense amplifiers, reducing line loading and enabling faster data rates (up to 8.0Gb/s/pin). The chip integrates a separated DFE architecture, input-offset calibration with majority voting, and a hybrid-loop DCC for high-speed operation, all within a 10×11mm² package.
Why Is the Symmetric-Mosaic Architecture Significant for Data Centers and AI?
Samsung’s symmetric-mosaic architecture is a game-changer for data centers and AI workloads, which demand ever-increasing memory density and bandwidth. The ability to produce 128GB DDR5 modules without TSV simplifies manufacturing and lowers costs. A single 32Gb-based 0.5TB DIMM consumes 30% less power than a 16Gb-based part, directly addressing the energy challenges of large-scale AI and big data operations.
How Does Samsung’s DDR5 Symmetric-Mosaic Architecture Impact Power and Efficiency?
By reducing the need for TSV and optimizing I/O line sharing, Samsung’s symmetric-mosaic DDR5 architecture cuts power consumption by about 10% compared to previous high-capacity modules. The improved efficiency not only lowers operating costs but also supports sustainability goals in hyperscale data centers and AI clusters.
Which DDR5 Module Configurations Are Enabled by Samsung’s New Architecture?
Samsung’s symmetric-mosaic DDR5 allows for a range of high-capacity DIMMs:
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32GB and 48GB in single-rank configurations
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64GB and 96GB in dual-rank configurations
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128GB modules without TSV
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Up to 1TB DIMMs using 3DS stacking
This flexibility meets the needs of servers, AI accelerators, and high-performance computing.
Chart: DDR5 Module Capacities Enabled by Symmetric-Mosaic Architecture
| Configuration | Capacity per Module | TSV Required? |
|---|---|---|
| Single-Rank | 32GB, 48GB | No |
| Dual-Rank | 64GB, 96GB | No |
| High-Capacity | 128GB | No |
| 3DS Stacked | Up to 1TB | Yes (3DS) |
What Are the Key Benefits of Samsung’s Symmetric-Mosaic DDR5 for the Industry?
Samsung’s symmetric-mosaic DDR5, as presented at ISSCC 2024, delivers:
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Double the density in the same form factor
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Up to 8.0Gb/s/pin data rates
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10% lower power consumption
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Elimination of TSV for 128GB modules
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Drop-in compatibility for existing systems
These advances help future-proof infrastructure for AI, machine learning, and cloud computing.
How Does Samsung’s Symmetric-Mosaic DDR5 Compare to Previous Generations?
Compared to 16Gb DDR5, Samsung’s symmetric-mosaic 32Gb DDR5 offers twice the capacity per chip, higher I/O speed, and lower energy use. It removes the complexity of TSV for most high-capacity modules, streamlining production and reducing costs for hyperscale deployments.
What Challenges Did Samsung Overcome to Achieve This DDR5 Breakthrough?
Samsung addressed challenges such as chip aspect ratio limits, package size constraints, and increased read latency. The symmetric-mosaic layout, combined with advanced calibration and error correction, allows high-density memory to fit within JEDEC standards while maintaining reliability and performance.
Buying Tips
When purchasing Samsung DDR5 modules with symmetric-mosaic architecture, use authorized distributors like Fly-wing Technology (HK) Co., Limited for genuine, competitively priced, and in-stock memory. Match module capacity and speed to your server or AI application needs. Leverage Fly-wing’s global sourcing for hard-to-find or high-capacity modules, and spend up to 70% of procurement time on standard parts for efficiency. Always verify compatibility and request technical documentation.
Electronic Components Expert Views
“Samsung’s symmetric-mosaic DDR5, showcased at ISSCC 2024, is a leap forward in memory technology-doubling capacity, reducing power, and simplifying module design. For data centers and AI, this means more performance per watt and unprecedented scalability, all within familiar form factors. It’s a pivotal moment for the memory industry.”
FAQ
How does Samsung’s symmetric-mosaic architecture double DDR5 capacity?
By partitioning logical banks and interleaving them, it fits twice the density into the same die size, enabling 32Gb chips.
What are the speed and power advantages of the new DDR5 chip?
It delivers up to 8.0Gb/s/pin and 10% lower power consumption compared to previous high-capacity DDR5 modules.
Do 128GB DDR5 modules require TSV with Samsung’s new architecture?
No, 128GB modules can be built without TSV, simplifying manufacturing and reducing costs.
Which applications benefit most from symmetric-mosaic DDR5?
AI, machine learning, big data, and cloud computing gain from higher capacity, lower power, and drop-in compatibility.
Where can I buy Samsung DDR5 symmetric-mosaic modules?
Fly-wing Technology (HK) Co., Limited provides global sourcing, competitive pricing, and technical support for Samsung’s latest DDR5 memory.
In our final ISSCC spotlight, we explore Samsung’s paper on a high-capacity, high-speed DDR5 memory that implements a monolithic-die-based 32-Gb DDR5 with 8 Gb/s/pin—all without leaving the 10 nm process.
The march of DDR5 performance continued at the recent IEEE International Solid-State Circuits Conference (ISSCC) with a paper by Samsung scientists.
Samsung aims to double DRAM capacity with its newly proposed architecture. Image (modified) used under Adobe Stock license
The paper, entitled “A 32-Gb 8.0-Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM process,” covers the limitations of the currently used 16-Gb architecture and Samsung’s proposed symmetric mosaic layout. In this article, we’ll summarize the key components of the architecture outlined in the paper.
From 16-Gb Die to Monolithic 32-Gb Die
Currently, the highest capacity DDR5 memories use a three-dimensional stacked (3DS) architecture based on a 16-Gb die and fabbed with a 10-nm process. The current mainstream end product is a 64-GB DDR5 DRAM module, with 128-GB modules increasing in demand.
The Samsung paper describes a monolithic 32-Gb high-density DDR5 die, still utilizing the 10-nm process. Samsung claims the 32-Gb die-based 3DS systems will improve performance, support memory up to 1 TB when used in eight die stacks, and achieve speeds of 8 Gb per second per pin.
The industry recognizes the need to move to a 32 Gb die. However, there are a number of obstacles. Nodes smaller than 10 nm for DRAM are not yet ready, so chipmakers must find ways to increase capacity without changing the fab process. Further, the current DRAM module form factor is too entrenched to increase package sizes without significantly increasing capacity or performance.
Mosaic Partitioning to Overcome Traditional DRAM Size Limits
The 32-Gb die will be an adaptation, not a new standard, and thus must accommodate conventional JDEC-dictated DDR5 form factor limits (10 mm x 11 mm maximum). Conventional methods for increasing capacity without decreasing process size involve adding DRAM cells within a bank or doubling the number of physical banks in a logical bank. This results in a rectangular memory footprint that exceeds the 10 mm x 11 mm package size bounding box in either the vertical or horizontal direction.
Comparison of die capacity increase with conventional methodology (left) and symmetric mosaic approach (right).
In the proposed architecture, each logical memory bank is broken into ? and ? partitions. These are interspaced as a symmetric mosaic of different partitions of the logical banks. This doubles DRAM capacity with only a 1.5 x horizontal and 1.33 x vertical area increase, which fits inside the bounding box.
Two partitions from different logical banks will share the same global I/O (GIO) signal line and sense amplifier. This sharing reduces the GIO line loading capacitance, boosting speeds and lowering power consumption. This physical layout keeps the I/O in the center, as is used in the 16-Gb die, shares the same pad structure, and utilizes a similar through-silicon via (TSV) structure to connect the 3DS layers.
Symmetric mosaic architecture.
The mosaic interleaving and sharing of the GIO line takes advantage of the precise timing of the guaranteed read-to-read and write-to-write timing specification (tCCD_L). The physical memory banks are divided and accessed as logical banks, with the tCCD_L characteristics used to dictate the timing.
Increasing Speed and Decreasing Interference
Keeping the data accurate at such high speeds requires extra logic for what is called decision feedback equalization (DFE). High speed digital is not the simple “on/off” voltage transition as is seen with lower speeds. Signals are rounded, interfered with, and often act more analog than digital. Signal line capacitance and resistance essentially create filters with R/C time constants that distort and impede the information-carrying signal (the symbol). The effects of one symbol can bleed into the next, or reflections from the receiving component can distort the symbol, causing inter-symbol interference (ISI), which must be mitigated to prevent invalid data.
Samsung’s proposed architecture adds to conventional DFE circuits with a four-tap system—an alternative to conventional two-tap DFE. In a DFE circuit, the taps are fed back to the input and summed. The four-tap directly feeds tap one back to minimize feedback delay. The second, third, and fourth taps use current model logic (CML) summation to further enhance the symbol accuracy.
(a) Four-tap DFE. (b) Tap one directly feeds the sampler. (c) Taps two through four into the CML circuit.
The DFE operates along with automatic-offset-voltage-calibration circuitry in the DQ buffers. The calibration circuit compensates for offset by using four paths for four phases of the operation and calibrates based on a direct majority voting of the four path outputs. The result is the ability to reliably operate at 8 Gb/s or faster.
Chip ID Pre-Decode
With double the RAM cells per die, power consumption becomes even more critical than with a 16-Gb die. Because these chips will largely be installed in 3D-stacked configurations, chipmakers must improve the process of targeting inefficient chips.
A “rank” is a logically combined set of physical banks that carry the same data word width as the on-die data bus. It can be formed within a physical die or across multiple dies in a 3D-stacked die system. For example, the upper left quadrant of each of eight-stacked dies could be combined into and addressed as one 8-bit logical rank.
In a standard configuration, a command comes into the command bus with a chip ID (CID). All ranks then perform decoding to see if they are the intended target. Once the decode is done, only the intended rank follows through. Having all ranks perform the decode operation wastes a significant amount of power.
(a) Traditional CID decode stack and (b) Samsung’s proposed pre-decode system.
This proposed architecture comes with a chip-ID-pre-decode in each rank. With such functionality, the primary rank has pre-decode circuitry before the TSV. It only sends the CID to the next rank if it is not the intended target. Essentially, each rank in the stack will stop the CID when it is the intended target. If the last rank in the stack is the intended target, no power is saved, but for all ranks below the top, a proportional amount of power is saved.
Progress Within Today’s Form Factor
Samsung’s proposed architecture significantly increases DRAM capacity without changing the overall form factor or decreasing chip etch geometries. By using a more efficient, though non-traditional, organization structure, more can be fit into the same area without standards or fab changes. The proposed architecture employs logical ranks, timing idiosyncrasies, and resource sharing to increase capacity, reduce power consumption, and increase maximum speed.
By Samsung’s measurements, a 32-Gb-based 0.5 TB DIMM consumes 30% less power than a 16-Gb-based part, making it a useful drop-in for data centers and other capacity- and power-hungry computing applications.
All technical images used courtesy of Samsung and ISSCC.
