Network-on-Chip (NoC) technology significantly enhances derivative System-on-Chip (SoC) designs by providing scalable, modular interconnect solutions that streamline integration, reduce design time, and improve performance. This approach is particularly beneficial for applications requiring rapid adaptation and deployment of SoCs, such as in AI, automotive, and consumer electronics.
What Is a Derivative SoC Design?
A derivative SoC design involves modifying an existing, proven SoC to create a new version that meets specific requirements without starting from scratch. This approach leverages the base design’s validated architecture, reducing development time and risk. Incorporating NoC technology into derivative designs allows for efficient scaling and integration of additional functionalities.
How Does NoC Enhance SoC Design Efficiency?
NoC technology enhances SoC design efficiency by providing a scalable and modular interconnect fabric that simplifies communication between various IP blocks. This reduces the complexity associated with traditional bus-based systems and allows for easier integration of new components. Tools like Arteris’ FlexNoC and Ncore facilitate this process by offering pre-verified interconnect solutions that can be reused across different designs.
Which Applications Benefit Most from NoC in Derivative SoCs?
Applications such as artificial intelligence, automotive systems, and consumer electronics benefit significantly from integrating NoC into derivative SoC designs. NoC enables efficient data transfer between cores and accelerators, essential for performance-intensive tasks like machine learning and real-time processing. For instance, Arteris’ NoC tiling methodology allows for scalable and modular designs suitable for AI applications.
Why Is NoC Tiling Important for SoC Scalability?
NoC tiling is crucial for SoC scalability as it allows designers to replicate modular units, or “tiles,” across the chip. Each tile is a self-contained functional unit, enabling faster integration, verification, and optimization. This approach reduces design time and risk, facilitating the development of large-scale SoCs.
How Does NoC Integration Affect Power Consumption?
Integrating NoC into SoC designs can lead to reduced power consumption by optimizing data routing and minimizing the need for long interconnects. This is particularly beneficial in applications where power efficiency is critical, such as mobile devices and automotive systems. NoC’s efficient communication pathways help in managing power distribution effectively across the chip.
What Are the Challenges in Implementing NoC in Derivative SoCs?
Implementing NoC in derivative SoCs presents challenges such as ensuring compatibility with existing IP blocks, managing the complexity of routing, and meeting performance targets. However, these challenges can be mitigated by using NoC solutions that offer flexibility and scalability, allowing for customization to meet specific design requirements.
Buying Tips
When selecting NoC solutions for derivative SoC designs, consider factors such as scalability, power efficiency, and compatibility with existing IP blocks. Arteris offers a range of NoC interconnect IPs, including FlexNoC and Ncore, which are designed to meet the demands of modern SoC architectures. These solutions provide pre-verified interconnect fabrics that can accelerate design time and reduce risk.
Electronic Components Expert Views
“Integrating NoC into derivative SoC designs is a strategic approach to enhance scalability and performance. It allows for efficient communication between components, reducing bottlenecks and enabling faster development cycles.”
FAQ
Q: What is a derivative SoC design?
A: A derivative SoC design involves modifying an existing SoC to create a new version that meets specific requirements, leveraging the base design’s validated architecture.
Q: How does NoC improve SoC designs?
A: NoC improves SoC designs by providing a scalable and modular interconnect fabric that simplifies communication between various IP blocks, reducing complexity and enhancing performance.
Q: What are the benefits of NoC tiling?
A: NoC tiling allows for scalable and modular designs by replicating functional units across the chip, reducing design time and risk while facilitating large-scale SoC development.
Q: How does NoC integration affect power consumption?
A: NoC integration can reduce power consumption by optimizing data routing and minimizing the need for long interconnects, leading to more efficient power distribution across the chip.
Q: What challenges are associated with implementing NoC in SoCs?
A: Challenges include ensuring compatibility with existing IP blocks, managing routing complexity, and meeting performance targets, which can be addressed by selecting flexible and scalable NoC solutions.
With the help of a case study, we examine how adopting NoC technology can significantly improve the process of updating existing chip designs.
When people talk about the creation of SoCs (systems-on-chips), they typically consider the tools, technologies, and flows associated with developing a new SoC from the ground up. Less discussed but equally important are the challenges associated with taking an existing SoC and using it as the foundation for a derivative design.
The idea of a derivative design is to modify a relatively small portion of a field-proven SoC, perhaps replacing one or more of its functions with upgraded offerings, while keeping the larger proportion of the design as-is. With users constantly requiring “more” in terms of performance and features and “less” in terms of power consumption and cost, derivative designs have the following advantages:
- Leveraging knowledge gained from the original.
- Minimizing cost.
- Limiting demands on resources.
- Reducing risk.
- Speeding time to market.
Creating an entirely new SoC is resource-intensive, time-consuming, and expensive by comparison. However, designing a derivative SoC isn’t without its own challenges, as we’ll soon see.
Complexities in SoC Designs
Let’s consider an example scenario where a portion of an existing SoC’s functionality needs to be replaced with new IP. Figure 1(a) shows an SoC with three IPs, each of which is equipped with one or two AXI ports. Note that these numbers are chosen purely for the sake of the example—a real-life SoC might comprise hundreds of IPs with several AXI ports apiece.
All on-chip communication between IPs is implemented using an AXI bus.
Figure 1. Creating a derivative SoC isn’t as easy as it seems.
Say we want to replace the original version of IP #3, which has two AXI ports, with the new incarnation in Figure 1(b), which has three AXI ports. We must also meet the following requirements:
- The replacement must occur quickly and efficiently, with minimal disruption to the existing silicon.
- The physical design for most of the SoC must remain unchanged.
Remember that the physical design includes any connections to the AXI bus. The bus can be as wide as 1,024 bits. For just one connection, you might need hundreds of wires for the data, control signals, and other connections—if you’re adding an extra port, you’re potentially adding thousands more wires to the design.
Ideally, we would pull out the old IP, drop in the new IP, and implement the physical design process only on the new IP. But how can we do so when increasing the number of ports? Let’s look at a real-life case study.
Upgrading to Dual Image Processing: A Case Study
Inuitive, an IC company specializing in vision-on-chip technology, decided to develop a derivative of their flagship product. The derivative design replaced one of the chip’s three vector cores with a new dual-image signal processor. Like in the example above, the new IP required a greater number of AXI ports than the original.
To address this challenge, they opted to employ a network-on-chip (NoC). An NoC is an advanced communication subsystem used within a semiconductor chip to connect components such as processors, memory blocks, and peripherals. Everything communicates with the NoC by means of sockets.
In a typical NoC realization, sockets accept parallel data from IPs and translate their protocols into a common packetized and serialized form that’s then transported throughout the NoC. Several packets can be transmitted simultaneously. When a packet arrives at its destination, the socket associated with the target translates it back into the protocol favored by that IP.
An NoC usually spans the entire SoC, facilitating communication across the chip. In this case, however, the team implemented a small, localized version of an NoC whose sole purpose was to connect the new IP into the existing SoC infrastructure. This approach, pictured in Figure 2, manages the addition of new components without the need for widespread modifications to the rest of the communication network. The NoC transfers data between the new IP, which has a greater number of AXI ports, and the initially configured AXI bus, which supports fewer ports.
Figure 2. Using an NoC to create a derivative SoC.
Rather than designing their own interconnect solution, which would have demanded a substantial investment of time and resources, the team decided to use FlexNoC interconnect IP. FlexNoC is a form of soft IP from Arteris. The designers used an associated tool to specify the required ports and NoC topology (star, ring, tree, mesh, etc.). The tool output the NoC as a register-transfer level (RTL) model, which then underwent synthesis and place-and-route along with the other soft IP functions.
This approach significantly sped up the market release of the new device. In the words of Dor Zepeniuk, the founder and CTO of Inuitive, “Using FlexNoC allowed us to get the NU4100 to market months earlier than if we had created a solution in-house.” It also provided data profiling capabilities, allowing for the detailed analysis and optimization of data traffic across the network. This played an important role in identifying bottlenecks and ensuring efficient data flow.
Advantages of Leveraging NoC Technology
Inuitive’s experience showcases the practical benefits of leveraging advanced NoC technology in SoC design. As SoCs increase in complexity, efficiently integrating new technologies and features becomes paramount. In that respect, NoCs are a game-changer. Using an NoC to implement a seemingly simple interface function might seem excessive, but in practice it’s a highly effective solution—especially compared to designing a new chip.
By making it easier to update a chip with only minimal changes to the overall system, NoC technology speeds up product development and encourages innovation. It reduces the need for comprehensive redesign, allowing companies to reallocate resources toward further innovation and exploring new market opportunities. For Inuitive, it also delivered enhanced product performance.
To learn more, visit the Innovative NoC Implementation Dramatically Speeds Derivative Design case study on the Arteris website.
Featured image background used courtesy of Adobe Stock<em>; all other images used courtesy of Arteris
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