What is the RISC-V Summit North America?
The RISC-V Summit North America is an annual event that brings together industry leaders, developers, and enthusiasts to discuss advancements in RISC-V technology, share innovations, and collaborate on the future of open-source hardware.
What were the major highlights of the recent summit?
Key highlights included significant announcements from companies like Andes Technology, RISC-V International, Arteris, and Codasip, showcasing the growing adoption and processing power of RISC-V architectures.
Which companies made notable announcements?
Andes Technology introduced new RISC-V cores, RISC-V International discussed ecosystem growth, Arteris unveiled interconnect IP solutions, and Codasip presented advancements in custom processor design.
Why is the RISC-V Summit significant for the tech industry?
The summit serves as a barometer for the health and direction of the RISC-V ecosystem, highlighting collaborative efforts, technological breakthroughs, and the increasing relevance of open-source hardware in various applications.
What Innovations Did Andes Technology Introduce?
Andes Technology announced the release of new high-performance RISC-V cores designed to enhance processing capabilities for AI and machine learning applications. These cores aim to provide improved energy efficiency and performance metrics, catering to the growing demand for intelligent edge devices.
Chart: Andes Technology’s New RISC-V Cores
| Core Model | Key Features | Target Applications |
|---|---|---|
| AX45MP | Multi-core support, AI-optimized | Edge AI, IoT devices |
| NX27V | Vector processing capabilities | High-performance computing |
How Is RISC-V International Expanding the Ecosystem?
RISC-V International highlighted the rapid growth of the RISC-V ecosystem, emphasizing collaborations with academic institutions, industry partners, and government agencies. Initiatives to standardize RISC-V extensions and improve software toolchains were discussed, aiming to make RISC-V more accessible and robust for developers worldwide.
What Solutions Did Arteris Present?
Arteris introduced advanced interconnect IP solutions tailored for RISC-V architectures. These solutions focus on enhancing system-on-chip (SoC) designs by providing scalable and efficient communication pathways between processors, memory, and peripherals, crucial for complex computing tasks.
How Is Codasip Advancing Custom Processor Design?
Codasip showcased its latest tools and methodologies for custom processor design, enabling developers to tailor RISC-V cores to specific application needs. By offering a high level of customization, Codasip aims to empower companies to optimize performance, power consumption, and area for their unique requirements.
Buying Tips
When considering RISC-V development boards or microcontrollers, assess the specific requirements of your project, such as processing power, peripheral support, and power consumption. Fly-Wing Technology (HK) Co., Limited offers a wide range of electronic components, including hard-to-find and obsolete parts, at competitive prices. With warehouses in Hong Kong and a global supplier network, they ensure quick and accurate sourcing to meet your procurement needs efficiently.
Electronic Components Expert Views
“The momentum behind RISC-V is undeniable. With open-source principles at its core, RISC-V is democratizing processor design, allowing for unprecedented innovation and customization in the semiconductor industry.”
FAQ
What is RISC-V?
RISC-V is an open-standard instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles, allowing for free and flexible processor design.
Why is RISC-V gaining popularity?
Its open-source nature enables customization, cost savings, and fosters innovation, making it attractive for academia, startups, and large corporations alike.
Can RISC-V compete with established architectures like ARM?
While ARM dominates many markets, RISC-V’s flexibility and growing ecosystem position it as a strong competitor, especially in emerging and specialized applications.
Where can I find RISC-V development tools?
Numerous vendors and distributors offer RISC-V development boards, compilers, and debugging tools, with Fly-Wing Technology being a notable source for various components.
Is RISC-V suitable for commercial products?
Yes, many companies are integrating RISC-V cores into commercial products, ranging from IoT devices to high-performance computing systems.
In this roundup, we delve into several announcements from the summit that are driving RISC-V adoption and enhancing processing power.
Four companies, including Andes Technology, RISC-V International, Arteris, and Codasip, made significant announcements at the RISC-V Summit in Santa Clara, California. The two-day summit served as a platform for education, information exchange, and discussions within the rapidly expanding RISC-V technical community.
Panelists at the RISC-V Summit
1. Andes Technology Invests in Automotive Safety
At the show, Andes unveiled a new automotive RISC-V processor, the AndesCore D45-SE, designed for ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.
Block diagram of AndesCore D45-SE
The AndesCore D45-SE is a 32-bit, eight-stage, dual-issue RISC-V processor designed for automotive applications. It is an enhanced version of the in-production D45 processor, featuring RISC-V GCBP extensions such as a single/double precision floating point unit, 16-bit compression, bit manipulation, and packed SIMD/DSP extensions.
The processor also includes Andes-specific extensions and safety features to meet certification requirements, such as an additional processor core and comparators for self-diagnosis, ECC memory error correction, bus protection, and hardware stack protection. The D45-SE achieves a benchmark of 6.12 Coremark/MHz, matching the performance of the conventional D45. Its two cores can operate independently, enhancing reliability and safety.
The D45-SE processor is suitable for critical automotive applications, including millimeter-wave radar sensors, around-view monitor systems (AVMS), vehicle instrument clusters, powertrain DCUs, infotainment DCUs, and front/rear differential applications.
2. RISC-V International Standardizes 64-bit With RVA23
The RISC-V International organization announced the ratification of RVA23, the 64-bit RISC-V implementation profile standard. This profile includes vector extensions designed for math-intensive workloads such as artificial intelligence/machine learning (AI/ML), cryptography, enterprise hardware systems, and operating systems. These new features are part of an effort to make RISC-V a viable option in more demanding settings.
While RISC-V offers flexibility in processor architecture design, this flexibility can lead to compatibility issues. Profiles ensure silicon commonality and software compatibility across different vendor implementations of the RISC-V instruction set architecture (ISA). The RVA23 profile achieves this for 64-bit RISC-V implementations. Software portability is crucial for the growth of RISC-V as a viable industry processor architecture. Although all RISC-V processors share some base architecture commonality, the specification includes both the base and many potential extensions. The profiles specify a set of mandatory extensions that all software developers can assume will be present. Non-mandatory extensions allow for customization for specific applications without compromising core standard functionality.
In addition to the math-intensive vector extensions, the RVA23 profile includes a hypervisor extension that supports virtualization—a key requirement for enterprise and cloud computing implementations.
3. Arteris Partners With SiFive for RISC-V SoC IP
Arteris announced the addition of the SiFive P870-D RISC-V CPU to its system-on-chip (SoC) IP library. This pre-verified solution minimizes design risk for data center hardware developers seeking to meet high-performance application requirements. The Arteris SoC is built on its proprietary scalable cache-coherent network-on-chip (NoC) interconnect IP, which reduces latency between processing units in the SoC. By integrating SiFive RISC-V IP with Arteris technology, SoC developers gain access to a pre-verified, high-performance RISC-V core option.
Pipeline diagram of SiFive’s P870
The Arteris/SiFive offering supports the advanced microcontroller bus architecture (AMBA) coherent hub interface (CHI) protocol, an open standard for chip interconnect specifications widely used in SoC solutions. SoCs often serve as the scaling arbiter for data center cluster systems. The high-speed AMBA CHI-compatible interconnect architecture and RISC-V core introduce data center-targeted SoC development to the RISC-V ecosystem. With built-in support, chip designers can be confident that the end result will offer familiarity, compatibility, and interoperability for data center buildouts.
4. Codasip Donates RISC-V CHERI SDK
Codasip announced the donation of its CHERI software development kit (SDK) to the community-interest organization CHERI Alliance. Capability Hardware Enhanced RISC Instructions (CHERI) is a security technology designed to protect systems against pointer-based memory attacks, which have accounted for approximately 70% of cyber-attacks over the past two decades.
The CHERI architecture extends standard RISC-V processor instruction set architectures (ISAs) to address the vulnerability of C language pointers. CHERI replaces pointers with alternatives that establish clear boundaries between different software functions. By isolating and replacing pointers, CHERI significantly reduces the vulnerability of C and C++ code to pointer-based memory attacks.
CHERI was originally developed as a joint research project between Cambridge University and SRI International. It has since received funding from the U.S. Defense Advanced Research Projects Agency (DARPA), UK Research and Innovation (UKRI), and other organizations. Codasip released a CHERI-compatible licensable processor in 2023. In its latest move, Codasip has donated its CHERI SDK to the CHERI Alliance to ensure broader availability to the RISC-V developer community.
