IDT71V424L12Y
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Category Integrated Circuits (ICs) / Memory
Description
J BEND 3-STATE 2009 Parallel (Memory Format) Memory 70C 3V 4194304bit 0.01A
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Technical Details
Physical
Surface Mount YES
Number of Pins 36
Technical
Published 2009
JESD-609 Code e0
Moisture Sensitivity Level (MSL) 3
Number of Terminations 36
ECCN Code 3A991.B.2.A
Terminal Finish Tin/Lead (Sn85Pb15)
Max Operating Temperature 70°C
Min Operating Temperature 0°C
HTS Code 8542.32.00.41
Subcategory SRAMs
Technology CMOS
Terminal Position DUAL
Terminal Form J BEND
Peak Reflow Temperature (Cel) 225
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 36
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Temperature Grade COMMERCIAL
Supply Voltage-Min (Vsup) 3V
Interface Parallel
Memory Type RAM, SRAM - Asynchronous
Supply Current-Max 0.155mA
Organization 512KX8
Output Characteristics 3-STATE
Memory Width 8
Standby Current-Max 0.01A
Memory Density 4194304 bit
Access Time (Max) 12 ns
I/O Type COMMON
Standby Voltage-Min 3V
Dimensions
Height Seated (Max) 3.683mm
Length 23.495mm
Width 10.16mm
Compliance
RoHS Status RoHS Compliant
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