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Package CDIP
Category Integrated Circuits (ICs) / Logic - Shift Registers
Description TRUE Contains Lead DUAL NEGATIVE EDGE shift register 125C 4.5V 30MHz 19.56mm
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Technical Details

Physical

Package / Case CDIP
Surface Mount NO

Technical

JESD-609 Code e0
Pbfree Code no
Number of Terminations 14
Terminal Finish TIN LEAD
Additional Feature SIPO OPERATION ALSO AVAILABLE
HTS Code 8542.39.00.01
Technology TTL
Terminal Position DUAL
Terminal Form THROUGH-HOLE
Peak Reflow Temperature (Cel) NOT SPECIFIED
Number of Functions 1
Supply Voltage 5V
Terminal Pitch 2.54mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Pin Count 14
Qualification Status Not Qualified
Operating Temperature (Max) 125°C
Operating Temperature (Min) -55°C
Supply Voltage-Max (Vsup) 5.5V
Temperature Grade MILITARY
Supply Voltage-Min (Vsup) 4.5V
Number of Bits 4
Family LS
Logic Function Shift Register
Output Characteristics 3-STATE
Output Polarity TRUE
Logic IC Type PARALLEL IN PARALLEL OUT
Trigger Type NEGATIVE EDGE
Propagation Delay (tpd) 30 ns
fmax-Min 30 MHz
Count Direction RIGHT

Dimensions

Height Seated (Max) 5.08mm
Length 19.56mm
Width 7.62mm

Compliance

RoHS Status Non-RoHS Compliant
Lead Free Contains Lead

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