74LV273N,112
RoHS 
RoHS compliant
RoHS compliantPackage 20-DIP (0.300, 7.62mm)
Category Integrated Circuits (ICs) / Logic - Flip Flops
Description
TRUE Not Qualified Master Reset D-Type Flip Flop -40C~125C TA 160muA 3.5pF 1V~5.5V
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Technical Details
Compliance
RoHS Status ROHS3 Compliant
Dimensions
Width 7.62mm
Length 26.73mm
Height Seated (Max) 4.2mm
Technical
Max Frequency@Nom-Sup 20000000Hz
fmax-Min 20 MHz
Propagation Delay (tpd) 24 ns
Input Capacitance 3.5pF
Trigger Type Positive Edge
Prop. Delay@Nom-Sup 24 ns
Max Propagation Delay @ V, Max CL 16ns @ 5V, 50pF
Number of Bits per Element 8
Max I(ol) 0.006 A
Output Polarity TRUE
Current - Output High, Low 12mA 12mA
Current - Quiescent (Iq) 160μA
Family LV/LV-A/LVX/H
Clock Frequency 100MHz
Load Capacitance 50pF
Supply Voltage-Min (Vsup) 1V
Power Supplies 3.3V
Supply Voltage-Max (Vsup) 5.5V
Number of Elements 1
Output Type Non-Inverted
Qualification Status Not Qualified
Function Master Reset
JESD-30 Code R-PDIP-T20
Base Part Number 74LV273
Time@Peak Reflow Temperature-Max (s) 30
Terminal Pitch 2.54mm
Supply Voltage 3.3V
Peak Reflow Temperature (Cel) 260
Terminal Position DUAL
Voltage - Supply 1V~5.5V
Technology CMOS
Subcategory FF/Latches
Terminal Finish NICKEL PALLADIUM GOLD
Type D-Type
Number of Terminations 20
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Part Status Obsolete
JESD-609 Code e4
Series 74LV
Published 1998
Packaging Tube
Operating Temperature -40°C~125°C TA
Physical
Surface Mount NO
Package / Case 20-DIP (0.300, 7.62mm)
Mounting Type Through Hole
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