EP20K200RC208-1V
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Category Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array)
Description
MACROCELL CMOS OTHER 2001 FPGA 85C 13kB 2.5ns 100MHz
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Technical Details
Physical
Mount Surface Mount
Technical
Published 2001
JESD-609 Code e0
Number of Terminations 208
ECCN Code 3A991
Terminal Finish TIN LEAD
Max Operating Temperature 85°C
Min Operating Temperature 0°C
HTS Code 8542.39.00.01
Subcategory Field Programmable Gate Arrays
Technology CMOS
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 2.5V
Terminal Pitch 0.5mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Pin Count 208
JESD-30 Code S-PQFP-G208
Number of Outputs 138
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 2.625V
Power Supplies 2.52.5/3.3V
Temperature Grade OTHER
Supply Voltage-Min (Vsup) 2.375V
Number of I/O 144
RAM Size 13kB
Clock Frequency 100MHz
Propagation Delay 2.5 ns
Number of Inputs 138
Programmable Logic Type LOADABLE PLD
Number of Logic Elements/Cells 8320
Number of Gates 526000
Number of Logic Blocks (LABs) 832
Output Function MACROCELL
Number of Dedicated Inputs 4
Dimensions
Height Seated (Max) 4.1mm
Length 28mm
Width 28mm
Compliance
RoHS Status RoHS Compliant
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