EP20K200EFC672-2X
RoHS
/
Package FBGA
Category Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array)
Description
MACROCELL CMOS OTHER 2001 FPGA 85C 13kB 1.97ns 205MHz
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Technical Details
Physical
Mount Surface Mount
Package / Case FBGA
Number of Pins 672
Technical
Published 2001
JESD-609 Code e0
Pbfree Code no
Moisture Sensitivity Level (MSL) 3
Number of Terminations 672
Terminal Finish Tin/Lead (Sn63Pb37)
Max Operating Temperature 85°C
Min Operating Temperature 0°C
HTS Code 8542.39.00.01
Subcategory Field Programmable Gate Arrays
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 220
Supply Voltage 1.8V
Terminal Pitch 1mm
Frequency 205MHz
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 672
Number of Outputs 368
Qualification Status Not Qualified
Power Supplies 1.81.8/3.3V
Temperature Grade OTHER
Max Supply Voltage 1.89V
Min Supply Voltage 1.71V
Memory Size 13kB
Number of I/O 376
RAM Size 13kB
Propagation Delay 1.97 ns
Frequency (Max) 170MHz
Programmable Logic Type LOADABLE PLD
Number of Logic Elements/Cells 8320
Number of Gates 526000
Number of Logic Blocks (LABs) 832
Output Function MACROCELL
Number of Dedicated Inputs 4
Dimensions
Height Seated (Max) 3.5mm
Length 27mm
Width 27mm
Compliance
RoHS Status RoHS Compliant
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