EP1810LC20T
RoHS
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Package /
Category Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array)
Description
MACROCELL CMOS COMMERCIAL Non-RoHS Compliant field programmable gate array 70C 22ns 50MHz 4.75V
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Technical Details
Physical
Surface Mount YES
Technical
JESD-609 Code e0
Pbfree Code no
Number of Terminations 68
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form J BEND
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch 1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 68
JESD-30 Code S-PQCC-J68
Qualification Status Not Qualified
Operating Temperature (Max) 70°C
Supply Voltage-Max (Vsup) 5.25V
Power Supplies 5V
Temperature Grade COMMERCIAL
Supply Voltage-Min (Vsup) 4.75V
Number of I/O 48
Clock Frequency 50MHz
Propagation Delay 22 ns
Organization 12 DEDICATED INPUTS, 48 I/O
Programmable Logic Type OT PLD
Output Function MACROCELL
Number of Macro Cells 48
JTAG BST NO
Number of Dedicated Inputs 12
In-System Programmable NO
Dimensions
Height Seated (Max) 5.08mm
Length 24.23mm
Width 24.23mm
Compliance
RoHS Status Non-RoHS Compliant
Alternative Model
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