GAL18V10B-20LP
RoHS
/
Package 20-DIP (0.300, 7.62mm)
Category Integrated Circuits (ICs) / Embedded - CPLDs (Complex Programmable Logic Devices)
Description
REGISTER PRELOAD; POWER-UP RESET 20-DIP (0.300 7.62mm) 2003 GAL18V10 complex programmable logic device 62.5MHz 115mA 26.125mm 20ns
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Technical Details
Physical
Mount Through Hole
Mounting Type Through Hole
Package / Case 20-DIP (0.300, 7.62mm)
Number of Pins 20
Technical
Operating Temperature 0°C~75°C TA
Packaging Tube
Published 2003
Series GAL?18V10
JESD-609 Code e0
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature REGISTER PRELOAD; POWER-UP RESET
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position DUAL
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 5V
Terminal Pitch 2.54mm
Reach Compliance Code not_compliant
Frequency 62.5MHz
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Base Part Number GAL18V10
Pin Count 20
Number of Outputs 10
Qualification Status Not Qualified
Power Supplies 5V
Programmable Type EE PLD
Max Supply Voltage 5.25V
Min Supply Voltage 4.75V
Number of I/O 10
Nominal Supply Current 115mA
Propagation Delay 20 ns
Turn On Delay Time 20 ns
Architecture PAL-TYPE
Output Function MACROCELL
Number of Macro Cells 10
Number of Dedicated Inputs 7
Voltage Supply - Internal 4.75V~5.25V
Number of Product Terms 96
Dimensions
Height Seated (Max) 4.57mm
Length 26.125mm
Width 7.62mm
Compliance
RoHS Status Non-RoHS Compliant
Lead Free Lead Free
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