EPM7256BFC100-7
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Category Integrated Circuits (ICs) / Embedded - CPLDs (Complex Programmable Logic Devices)
Description
MACROCELL Not Qualified CMOS EE PLD CPLD 2.5V 1.8/3.32.5V 7.5ns 11mm
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Technical Details
Physical
Surface Mount YES
Technical
JESD-609 Code e0
Moisture Sensitivity Level (MSL) 3
Number of Terminations 100
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature YES
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 220
Supply Voltage 2.5V
Terminal Pitch 1mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Pin Count 100
JESD-30 Code S-PBGA-B100
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 2.625V
Power Supplies 1.8/3.32.5V
Supply Voltage-Min (Vsup) 2.375V
Number of I/O 84
Clock Frequency 126.6MHz
Propagation Delay 7.5 ns
Organization 4 DEDICATED INPUTS, 84 I/O
Programmable Logic Type EE PLD
Output Function MACROCELL
Number of Macro Cells 256
JTAG BST YES
Number of Dedicated Inputs 4
In-System Programmable YES
Dimensions
Height Seated (Max) 1.7mm
Length 11mm
Width 11mm
Compliance
RoHS Status Non-RoHS Compliant
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