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Package TSSOP
Category Integrated Circuits (ICs) / Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Description LVDS TSSOP PLL BASED CLOCK DRIVER e3 clock generator circuit 3.465V 204MHz 6.5mm 0C
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Technical Details

Physical

Mount Surface Mount
Package / Case TSSOP

Technical

Published 2007
JESD-609 Code e3
Pbfree Code yes
Number of Terminations 24
Terminal Finish MATTE TIN
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 24
JESD-30 Code R-PDSO-G24
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.465V
Temperature Grade COMMERCIAL
Number of Circuits 1
Frequency (Max) 204MHz
Family 874S
Input LVDS
Logic IC Type PLL BASED CLOCK DRIVER
fmax-Min 8.75 MHz
Number of True Outputs 1

Dimensions

Length 6.5mm
Width 4.4mm

Compliance

RoHS Status RoHS Compliant

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