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Package TSSOP
Category Integrated Circuits (ICs) / Clock/Timing - Clock Buffers, Drivers
Description LVTTL TSSOP R-PDSO-G20 Matte Tin (Sn) - annealed clock buffer 4.4mm 3.3V 0.035ns 266MHz
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Technical Details

Physical

Mount Surface Mount
Package / Case TSSOP

Technical

Published 2012
JESD-609 Code e3
Pbfree Code yes
Moisture Sensitivity Level (MSL) 1
Number of Terminations 20
Terminal Finish Matte Tin (Sn) - annealed
Max Operating Temperature 70°C
Min Operating Temperature 0°C
Subcategory Clock Drivers
Technology CMOS
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count 20
JESD-30 Code R-PDSO-G20
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.465V
Power Supplies 3.3V
Temperature Grade COMMERCIAL
Number of Circuits 1
Frequency (Max) 266MHz
Family 8525
Input LVTTL
Logic IC Type LOW SKEW CLOCK DRIVER
Same Edge Skew-Max (tskwd) 0.035 ns
Number of True Outputs 4

Dimensions

Length 6.5mm
Width 4.4mm

Compliance

RoHS Status RoHS Compliant

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